1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and a data write method thereof and more particularly to a semiconductor integrated circuit device using a DRAM (Dynamic Random Access Memory) or FeRAM (Ferro-electric Random Access Memory) in a memory core section.
2. Description of the Related Art
Conventionally, pseudo SRAMs each using a DRAM (Dynamic Random Access Memory) or FeRAM (Ferro-electric Random Access Memory) in a memory core section are commercialized in order to enhance the integration density while the compatibility thereof with existing SRAMs (Static Random Access Memories) in application is maintained.
Among the pseudo SRAMs, a synchronous type SRAM in which an internal circuit is controlled by a clock signal internally and time-serially generated based on an external input signal (for example, external chip enable signal /CE) and an asynchronous type SRAM in which an internal circuit can be operated asynchronously with respect to an external input signal are provided. At present, the synchronous type SRAM is dominant, but expectations for the asynchronous type SRAM gradually rise.
In the synchronous type pseudo SRAM, a high-speed operation mode such as a static column mode in which memory cells of a row selected by a row address are sequentially accessed by use of a column address signal is provided in many cases.
In the static column mode, the address data latching operation is not performed to cope with the asynchronous operation in the read operation. Further, the address latch control operation is performed by use of an external write enable signal /WE in order to prevent destruction of data in the write operation (refer to FIG. 18).
The reason why the address latch control operation at the write operation time is required is as follows. In the read operation, cell data is simply read out even when column selection lines are multi-selected, and therefore, data stored in the cell will not be destroyed by rewriting data which is the same as the read data after the read operation. However, in the write operation, if the column selection lines are multi-selected, there occurs a possibility that erroneous data will be written into a cell and thus correct data stored in the cell will be rewritten.
Therefore, in the synchronous write operation of the static column, the clock operation for the column address signal and external write enable signal /WE is required in order to prevent data destruction and therefore a complete asynchronous operation is not performed.
In the asynchronous type pseudo SRAM, a semiconductor integrated circuit device in which a high-speed operation mode such as a static column mode can be set is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2002-269977.
However, like the synchronous type pseudo SRAM, since the asynchronous type pseudo SRAM requires the clock operation for the column address signal and external write enable signal /WE in the write operation of the static column mode, a complete asynchronous operation is not performed.
As described above, in the conventional semiconductor integrated circuit device having the synchronous or asynchronous type pseudo SRAM mounted thereon, it is difficult to realize a complete asynchronous operation with respect to an external input signal while data is prevented from being destroyed in the write operation of the high-speed operation mode such as a static column mode.